RESERVE MY SPOT

Mikhail received his computer science and applied mathematics master’s degree in 2007 followed by mathematics and physics Ph. D in 2011 from Lomonosov Moscow State University. His main research interests are in the fields of discrete mathematics, control systems theory, computational and systems biology.

He currently occupies position of Associate Professor at Mathematical Cybernetics department of Lomonosov Moscow State University, where he co-supervises master’s programme in the field of computer-aided tools development for modern integrated circuits design. He also works as scientific consultant at Ajinomoto-Genetika-Research Institute, where he is involved in research of mathematical modelling of cell metabolic fluxes with the help of data, acquired from heavy isotopes tracer experiments.

• Understanding fundamentals of digital hardware design

• Good knowledge of Verilog HDL

• Skills of digital hardware prototyping with FPGAs

• Knowledge of assembly languages and basic skills of MIPS assembly programming

• Good knowledge of the basic principles of modern hardware architecture

SKILLS:

- Algorithms

- Software Engineering

- Applied Mathematics

Mathematical Modeling

- Software Development

- C++

- Data Structures

DATE: 7 - 27 Jul, 2018

DURATION: 3 Weeks

LECTURES: 3 Hours per day

LANGUAGE: English

LOCATION: Barcelona, Harbour.Space Campus

COURSE TYPE: Offline

WHAT YOU WILL LEARN
COURSE OUTLINE
ABOUT MIKHAIL
BIBLIOGRAPHY
HARBOUR.SPACE 

COMPUTER ORGANISATION AND SYSTEMS 

The module’s goal is to give basic knowledge of computer systems organisation and design. Understanding architecture and design process of microprocessors and other digital microelectronic devices is at the core of the module. First week’s materials covers Verilog hardware definition language (HDL), modern design flow of microelectronic devices and their basic components. During the week, students have hands on experience with prototyping microelectronic devices with field-programmable gate arrays (FPGAs). During second week, common essentials of synchronous circuits design are covered. Students learn how to implement algorithms directly in hardware and how simple microprocessor is designed. Third week is devoted to more advanced topics in
computer architecture, including pipelined processors,
caches and virtual memory design. All covered topics are supported with design or programming labs using Quartus software suite and Altera-Intel FPGAs.

MIKHAIL 
SHUPLETSOV

RESERVE MY SPOT

We offer innovative university degrees taught in English by industry leaders from around the world, aimed at giving our students meaningful and creatively satisfying top-level professional futures. We think the future is bright if you make it so.

HARBOUR.SPACE UNIVERSITY

DATE: 7 – 27 Jul, 2018

DURATION:  3 Weeks

LECTURES: 3 Hours per day

LANGUAGE: English

LOCATION: Barcelona, Harbour.Space Campus

COURSE TYPE: Offline

COMPUTER ORGANISATION AND SYSTEMS 

Session 2

From transistors to Boolean circuits.

Boolean functions and algebras. Complementary metal oxide semiconductor (CMOS) transistors. Modelling CMOS transistors with Boolean functions. CMOS circuits. Logic gates. Boolean circuits and combinational logic design. Simple combinational blocks.


Seminar: representing Boolean functions.


Representing Boolean functions with CMOS circuits. Representing Boolean functions with Boolean circuits: sum-of-products and product-of-sums forms. Logic minimisation with Karnaugh Maps.

Session 3

Introduction to hardware description languages.

The Verilogmeterized modules. Module hierarchy. Continuous assignment. Operators that generate combinational circuits. Always and initial blocks. Blocking and non-blocking assignment.


Lab: hardware simulation with ModelSim.
Basics of Verilog’s module simulation with ModelSim software. Reading waveforms. Creating simple testbenches with Verilog.

Presentation of the first week’s project.

Session 4

Digital building blocks.

Arithmetic circuits: adders, substractors, comparators, shifters and rotators. Circuits for multiplication and integer division. Building arithmetic-logic unit (ALU). Fixed and floating-point number systems. Implementing arithmetic operations in fixed and floating-point systems. How elementary functions (sin, cos, tan and etc.) are implemented in hardware.

Lab: designing ALU


Creating a simple ALU. Extending ALU with new operations. Simulating ALU in ModelSim and prototyping with FPGA.

SHOW MORE

Session 1

Introduction

Microelectronics and semiconductor industry. Electronic Design Automation (EDA). Semiconductor intellectual property (IP). Abstractions hierarchy and modelling approaches
for modern microelectronic devices. Typical
design flow of digital microelectronic devices. Application-specific integrated circuit (ASIC) and field­programmable gate array (FPGA). Design
quality measures of digital microelectronic devices.

Lab: introduction to FPGA design using Quartus software.


Quartus interface fundamentals. Pin assignment. Basic FPGA design flow. The IP catalog. Using the schematics editor. Implementing a simple counter in FPGA.

All rights reserved. 2018

Harbour.Space University
Tech Heart
SUBMIT


The module’s goal is to give basic knowledge of computer systems organisation and design. Understanding architecture and design process of microprocessors and other digital microelectronic devices is at the core of the module. First week’s materials covers Verilog hardware definition language (HDL), modern design flow of microelectronic devices and their basic components. During the week, students have hands on experience with prototyping microelectronic devices with field-programmable gate arrays (FPGAs). During second week, common essentials of synchronous circuits design are covered. Students learn how to implement algorithms directly in hardware and how simple microprocessor is designed. Third week is devoted to more advanced topics in computer architecture, including pipelined processors, caches and virtual memory design. All covered topics are supported with design or programming labs using Quartus software suite and Altera-Intel FPGAs.

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