Finite State Machines.

Formal definition and semantics of finite state machines (FSMs). Types of FSMs: Moore and Mealy Machines, nondeterministic FSMs. Representations of FSM: state tables, diagrams and equations, sequential circuits. State encodings. Building sequential circuit from state diagram. Building FSM from schematics. Factoring FSMs. Examples. State minimisation problem. Moore's theorem.

Lab: Implementing FSMs in hardware.

Using behavioral Verilog to model FSM. Implementing simple FSMs with FPGA.

Hardware implementation of algorithms and data structures.

Datapath and control. Reasoning in terms of states and transitions. Selecting blocks for the datapath. Concurrency and parallelism in the datapath. Designing control. Examples. Performance analysis. How stacks and queues are implemented in hardware. Performance tradeoffs.

Lab: implementing algorithm in hardware.

Creating FPGA implementation of an algorithm. Performance analysis and optimisation.

Sequential digital building blocks.

Sequential logic: latches and triggers. Timing characteristics of sequential circuits: set-up and hold time, clock period and frequency. Transistor and gate-level modelling of basic sequential circuits. Synchronous and asynchronous circuits. Registers and memory arrays. Register file.

Lab: designing sequential digital blocks.

Designing simple latches and triggers with structural Verilog and implementing them with FPGA.

Presentation of the first week’s project.

Timing analysis.

Static and dynamic timing analysis. Required and actual arrival time, timing slack. Setup and hold time violations, clock skew. Glitches. Critical paths. Detecting false critical paths.

Lab: Timing analysis.

Timing accurate simulation in ModelSim. Specifying timing constraints. Performing static timing analysis with TimeQuest.

Assembly and machine language.

MIPS assembly language. Core MIPS instructions. Type of operands: registers, memory and constants. MIPS machine language. R-type, I-type and J-type instructions. Basics of programming in assembly programming.

Seminar: programming in assembly.

Writing simple programmes in MIPS assembly language. Creating a simple translator from high-level language (e.g. subset of Python or C language) to MIPS assembly language.

Microarchitecture.

Architectual state and instruction set. Designing single cycle processor. Basic elements of the datapath. Assembling data path to support basic MIPS instructions. Single-cycle control. Performance analysis.

Lab: building a microprocessor.

Adding support for new instructions to the single-cycle processor, timing analysis of single cycle processor. Simulating microprocessor with a sample programme. Prototyping microprocessor with FPGA.

Presentation of the second week’s project.

Microarchitecture continued.

Designing multi-cycle processor. Non-architectual state. Modifying datapath for multicycle support. Multi-cycle control. Comparing performance of single and multi-cycle processors.

Lab: multi-cycle processor

Designing a multi-cycle processor. Timing analysis of mulitcycle processor and comparison with single-cycle processor.

Pipelined processors.

Pipelined datapath and control. Hazards. Data hazards: forwarding and stalls. Branch hazards: flushing. Modifying instruction set to support processor pipeline. Performance analysis.

Lab: designing pipeline

Designing simple pipelined processor with hazards control unit. Writing testbenchs for control and data hazards. Running simple programmes on pipelined processor.

Caches.

The basics of caches. Cache data storage, retrieval and replacement strategies. Advanced cache design. The evolution of MIPS caches.

Lab: designing a cache.

Designing a memory cache. Integrating it with microprocessor. Evaluating performance of different cache strategies.

Virtual Memory.

Address translation. The page table. The translation lookaside buffer. Memory protections. Replacement strategies. Multilevel page tables.

Lab: designing MMU.

Designing a memory management unit (MMU) with virtual memory and cache support.

Introduction

Microelectronics and semiconductor industry. Electronic Design Automation (EDA). Semiconductor intellectual property (IP). Abstractions hierarchy and modelling approaches
for modern microelectronic devices. Typical
design flow of digital microelectronic devices. Application-specific integrated circuit (ASIC) and field­programmable gate array (FPGA). Design
quality measures of digital microelectronic devices.

Lab: introduction to FPGA design using Quartus software.

Quartus interface fundamentals. Pin assignment. Basic FPGA design flow. The IP catalog. Using the schematics editor. Implementing a simple counter in FPGA.

Introduction to hardware description languages.

The Verilogmeterized modules. Module hierarchy. Continuous assignment. Operators that generate combinational circuits. Always and initial blocks. Blocking and non-blocking assignment.

Lab: hardware simulation with ModelSim.
Basics of Verilog’s module simulation with ModelSim software. Reading waveforms. Creating simple testbenches with Verilog.

Presentation of the first week’s project.

Digital building blocks.

Arithmetic circuits: adders, substractors, comparators, shifters and rotators. Circuits for multiplication and integer division. Building arithmetic-logic unit (ALU). Fixed and floating-point number systems. Implementing arithmetic operations in fixed and floating-point systems. How elementary functions (sin, cos, tan and etc.) are implemented in hardware.

Lab: designing ALU

Creating a simple ALU. Extending ALU with new operations. Simulating ALU in ModelSim and prototyping with FPGA.

From transistors to Boolean circuits.

Boolean functions and algebras. Complementary metal oxide semiconductor (CMOS) transistors. Modelling CMOS transistors with Boolean functions. CMOS circuits. Logic gates. Boolean circuits and combinational logic design. Simple combinational blocks.

Seminar: representing Boolean functions.

Representing Boolean functions with CMOS circuits. Representing Boolean functions with Boolean circuits: sum-of-products and product-of-sums forms. Logic minimisation with Karnaugh Maps. 

I/O systems

Basic input and output systems. General purpose digital I/O. Serial I/O. The SPI and UART protocols.

Lab: interfacing microprocessor.

Loading programme into microprocessor memory via UART. Designing a simple hardware text processor.

Presentation of the third week’s project.