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Mikhail received his computer science and applied mathematics master’s degree in 2007 followed by mathematics and physics Ph.D in 2011 from Lomonosov Moscow State University.

His main research interests are in the fields of discrete mathematics, control systems theory, computational and systems biology.

He currently occupies position of Associate Professor at Mathematical Cybernetics department of Lomonosov Moscow State University, where he co-supervises master’s programme in the field of computer-aided tools development for modern integrated circuits design.

He also works as scientific consultant at Ajinomoto-Genetika-Research Institute, where he is involved in research of mathematical modelling of cell metabolic fluxes with the help of data, acquired from heavy isotopes tracer experiments.

- Understanding fundamentals of digital hardware design

- Basic knowledge of Verilog HDL


- Skills of digital hardware prototyping with FPGAs


- Understanding of assembly language and basic skills of MIPS assembly programming


- Basic knowledge of modern hardware architecture

SKILLS:

- Algorithms

Teaching

- Software Engineering

- Applied Mathematics

- Research

- LaTeX

- Mathematical Modeling

- C++

DATE: 10 Jun - 28 Jun, 2019

DURATION: 3 Weeks

LECTURES: 3 Hours per day

LANGUAGE: English

LOCATION: Barcelona, Harbour.Space Campus

COURSE TYPE: Offline

WHAT YOU WILL LEARN
COURSE OUTLINE
ABOUT MIKHAIL
BIBLIOGRAPHY
HARBOUR.SPACE 

The module’s goal is to give basic knowledge of computer systems organisation and design. Understanding architecture and design process of microprocessors and other digital microelectronic devices is at the core of the module.

The first week’s materials covers Verilog hardware definition language (HDL), modern design flow of microelectronic devices. During the week, students learn basic components of modern computer systems, common essentials of synchronous circuits design and have hands-on experience with prototyping simple microelectronic control systems with the help of field-programmable gate arrays (FPGAs).

The third week is devoted to the basic principles of computer architecture and assembly languages. During this week students learn the fundamentals of MIPS assembly language, analyse and modify the structure of a simple MIPS-based microprocessor. All covered topics are supported with design or programming labs using Quartus software suite and Altera-Intel FPGAs.

MIKHAIL 
SHUPLETSOV
RESERVE MY SPOT

We offer innovative university degrees taught in English by industry leaders from around the world, aimed at giving our students meaningful and creatively satisfying top-level professional futures. We think the future is bright if you make it so.

HARBOUR.SPACE UNIVERSITY

DATE: 10 Jun – 28 Jun, 2019

DURATION: 3 Weeks

LECTURES: 3 Hours per day

LANGUAGE: English

LOCATION: Barcelona, Harbour.Space Campus

COURSE TYPE: Offline

FOUNDATIONS
OF JAVA

Session 2

From transistors to Boolean circuits
Boolean functions and algebras. Complementary metal oxide semiconductor (CMOS) transistors. Modelling CMOS transistors with Boolean functions. CMOS circuits. Logic gates. Boolean circuits and combinational logic design. Simple combinational circuits.

Seminar: representing Boolean functions
Representing Boolean functions with CMOS circuits. Representing Boolean functions with Boolean circuits: sum-of-products and product-of-sums forms. Logic minimisation with Karnaugh Maps.

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Session 1

Introduction
Quick review of computer history: from early calculators to modern computers. How computers are made: microelectronics and semiconductor industry. Electronic Design Automation (EDA). Semiconductor intellectual property (IP). Abstractions hierarchy and modelling approaches for modern microelectronic devices. Typical design flow of digital microelectronic devices. Application-specific integrated circuit (ASIC) and field-­programmable gate array (FPGA). Design quality measures of digital microelectronic devices.

Lab: introduction to FPGA design using Quartus software
Quartus interface fundamentals. Pin assignment. Basic FPGA design flow. The IP catalogue. Using the schematics editor. Implementing a simple counter in FPGA.

All rights reserved. 2018

Harbour.Space University
Tech Heart

The module’s goal is to give basic knowledge of computer systems organisation and design. Understanding architecture and design process of microprocessors and other digital microelectronic devices is at the core of the module.

The first week’s materials covers Verilog hardware definition language (HDL), modern design flow of microelectronic devices. During the week, students learn basic components of modern computer systems, common essentials of synchronous circuits design and have hands-on experience with prototyping simple microelectronic control systems with the help of field-programmable gate arrays (FPGAs).

The third week is devoted to the basic principles of computer architecture and assembly languages. During this week students learn the fundamentals of MIPS assembly language, analyse and modify the structure of a simple MIPS-based microprocessor. All covered topics are supported with design or programming labs using Quartus software suite and Altera-Intel FPGAs.

HOW COMPUTERS WORK
HOW 
COMPUTERS 
WORK

Session 3

Introduction to hardware description languages
The Verilog HDL. Simulation and synthesis. Behavioural and structural representations of hardware. Basic data structures: wire and reg. Modules: ports, declaration and instances. Continuous assignment. Operators that generate combinational circuits. Always and initial blocks. Blocking and non-blocking assignment.

Lab: hardware simulation with ModelSim
Basics of Verilog’s module simulation with ModelSim software. Reading waveforms. Creating simple testbenches with Verilog.

Session 4

The Verilog HDL continued
Parameterised modules. Module hierarchy. Generate blocks.

Lab: Verilog coding essentials
Creating behavioural descriptions: assign and always statements. Creating structural descriptions: gate-level modelling, creating modules hierarchies. Practice with parameterised modules and generate blocks.

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